This invention relates to a process for making silicon integrated circuits with double metal layers, and more particularly to such a process in which the steps for forming the inter metal layer insulation includes etching back in one step a stack of insulation layers overlying the first metal layer, which stack is composed of a deposited silicon dioxide layer, a spun and cured silica coat and a photoresist layer to provide a nearly planar surface on which to deposit the outer metal layer.
Planarizing processes for forming multiple metal layer conductor systems in integrated circuits have been used for several years. One of the first commercially successful of such processes includes the steps of depositing a first silicon dioxide layer by a standard chemical vapor deposition (CVD) step, spinning on and curing a photoresist and etching back the photoresist and the deposited oxide at about the same rate. The etching is stopped at the point or before the point at which the photoresist is completely removed. The first blanket oxide layer is thinned especially at thick regions but is not penetrated anywhere.
However, poor reproducibility and control was realized arising from the sensitivity of the photoresist etch rate to variations in cure cycle parameters. Also resist coverage is relatively thick and tends to fill in areas of dense metal patterns. Typically such etchbacks must be repeated two or more times to achieve a significant etching and planarizing of the deposited silicon dioxide. Further, photoresists have poor dielectric properties and any residual photoresist that is left in the intermetal layer insulation system degrades the dielectric performance and reliability of the system.
In a more recent double-metal planarization process, illustrated herein in FIGS. 1a, 1b and 1c, the interlayer dielectric between first metal films (22a and 22b) and second metal film 18 is composed of first (12) and second (14) deposited silicon dioxide layers having a layer of spin on glass (16) therebetween. The term "spin on glass" (SOG) is used in the art to mean a spun on coat of an organic liquid precursor of silica that is subsequently heated and transformed to a silica coat, whereas a more accurate term would be "spin on silica". The thickness of the spin on glass, silica coat (16), is lowest over broad or spaced apart first metal runs (22a and 22b), and tends to thicken in the gaps between closely spaced first metal runs (22a and 22b) and to mound over such high density networks of fine-line first metal conductors. The spin on glass 16 is etched back. It is first removed in the thinnest areas and in those areas the etchant removes some of the first deposited oxide layer 12. The etching is stopped only after all the spin on glass is removed. Thus the first deposited oxide layer 12 is planarized to a degree and deposition of second metal 14 is accomplished with better physical integrity of the metal where crossing over first metal runs (22a and 22b). In this process, the spin on glass is used only as a sacrificial layer.
Another and similar double metal planarization process subtitutes spin on polyimide between the first and second deposited silicon dioxide layers. Etch-back of the polyimide and first oxide layers is effected in the same fashion except the etching is terminated before all of the polyimide layer is removed. Other and similar double metal planarization processes use the sandwiched spin on glass coat but do not remove all of it.
In the above-described double metal processes, the photoresist, or spin on glass or polyimide in each case is at least partially sacrificed, i.e. removed. In each case, the greater the amount left in the integrated circuit of the sacrificial material, the more planar is the insulation surface on which the second metal layer is to be deposited. On the other hand, residual amounts of organic materials in the otherwise inorganic structure of the integrated circuit is liable to degrade the physical and dielectric properties of the insulation layer with time.
Another limitation on planarizing processes relying upon the use of layers that are sacrificed at an etch-back step, is that the best known sacrificial layer materials such as organic resins and spun on liquid and cured silica coats must be removed entirely in the aforementioned regions of greatest start planarity where vias are to be made for interconnecting the multiple metal films with each other and/or the substrate. Remaining spin on glass is hygroscopic. The water in such glass and the volatized components of the organic vehicle residue at a via cause delamination of the second non-sacrificial insulation layer. Furthermore, aluminum does not adhere well to spin on glass also degrading the integrity of an aluminum filled via.
It is an object of this invention to provide a double metal conductor system in a silicon integrated circuit leading to an improved planarity in the inter metal insulation without leaving sacrificial layer material in the inter metal insulation.